1. Field of the Invention
This invention relates to a dynamic semiconductor memory device, and more particularly to reduction of occupation area thereof and improvement in operation speed thereof.
2. Description of the Prior Art
An exemplary one of dynamic semiconductor memory devices is a serial access memory which generally has such a common construction as shown in FIG. 3.
Referring to FIG. 3, the serial access memory device shown includes a memory cell array 61 in which a plurality of memory cells of the three-transistor type are arranged in l row and m columns. A memory cell of the memory cell array 61 to which data is to be written is selected by a write row selecting ring pointer 62 and a write column selecting ring pointer 64. Meanwhile, a memory cell of the memory cell array 61 from which data is to be read out is selected by a read row selecting ring pointer 63 and a read column selecting ring pointer 65. The write column selecting ring pointer 64 includes a write control circuit (not shown in FIG. 3) while the read column selecting ring pointer 65 includes a read control circuit (not shown in FIG. 3).
A serial access memory is generally constructed such that memory cells of a memory array thereof are accessed in a predetermined order. Thus, in such a serial access memory as shown in FIG. 3, access to the memory cell array proceeds in such an order as illustrated in FIG. 4. In particular, at first, memory cells in the first column are accessed in an order beginning with a memory cell in the first row and ending with another cell in the l-th row. Then, the memory cells in the second column are accessed in a similar order beginning with a memory cell in the first row and ending with another memory cell in the l-th row. Memory cells in the other columns are accessed in a similar manner until a memory cell in the l-th row in the m-th column is accessed, and after then, the memory cells of the memory cell array are accessed in the same order beginning with the memory cells in the first row in the first column.
In operation, the write row selecting ring pointer 62 and the write column selecting ring pointer 64 are initialized in response to a write reset signal WRST received from an external signal source (not shown), and the read row selecting ring pointer 63 and the read column selecting ring pointer 65 are initialized in response to a read reset signal RRST also received from the external signal source. As a result of such initialization, the first row in the first column of the memory cell array 61 is designated. Then, the second, third, . . . and l-th row in the first column are designated sequentially and after then, the first, second, . . . , and l-th row in the second column are designated sequentially in response to write clocks WCLK or read clocks RCLK received from another external signal source (not shown). Thus, after the l-th row in the m-th column is designated, the first row in the first column is designated again, and after then, similar addressing is repeated until another write reset signal WRST or another read reset signal RRST is received. Input data DI is written by the write control circuit in the write column selecting ring pointer 64 to a memory cell designated by the write row selecting ring pointer 62 and the write column selecting ring pointer 64. To the contrary, information stored in a memory cell designated by the read row selecting ring pointer 63 and the read column selecting ring pointer 65 is read out as output data DO from the read control circuit in the read column selecting ring pointer 65. Writing operation and reading operation are performed independently of each other.
Referring now to FIG. 5 which schematically illustrates detailed construction of essential part of the serial access memory shown in FIG. 3, a write bit line WB.sub.k and a read bit line RB.sub.k are provided for each column of the memory cell array 61, where k is any integer from 1 through m. A write driver 11 is connected to each write bit line WB.sub.k while a read circuit 13 is connected to each read bit line RB.sub.k. Meanwhile, a write word line WWL.sub.n and a read word line RWL.sub.n are provided for each row of the memory cell array 61, where n is any integer from 1 through l. A write selecting gate 12 in the form of an AND gate is provided for each memory cells 10 of the memory cell array 61. Thus, the memory cells 10 in the n-th, (n+1)th and (n+2)th rows in the k-th, and (k+1)th columns of the memory cell array 61 can be seen in FIG. 5. Each of the memory cells 10 includes three N-channel MOS field effect transistors 1, 2 and 3. Each of the memory cells 10 further includes a storage capacitor 4.
Here, the memory cell 10, for example, in the n-th row in the k-th column is considered The transistor 3 of the memory cell 10 considered is connected at the gate thereof to the write bit line WB.sub.k by way of the transistor 1, at the drain thereof to the read bit line RB.sub.k by way of the transistor 2, and at the source thereof to the ground. The transistor 1 is connected at the gate thereof to an output of the write selecting gate 12. The transistor 2 is connected at the gate thereof to the read word line RWL.sub.n. The write selecting gate 12 is connected at one of a pair of input terminals thereof to the write word line WWL.sub.n which is in turn connected to the write row selecting ring pointer 62 shown in FIG. 3. The read word line RWL.sub.n is connected to the read row selecting ring pointer 63.
The write selecting gates 12 in each of column are connected to receive at the other respective input terminals thereof a write column selecting signal WBS.sub.k from the write column ring pointer 64. Meanwhile, the read circuit 13 in each column is connected to receive a read column selecting signal RBS.sub.k from the read column selecting ring pointer 65.
In writing operation, when a memory cell 10 for example, in the n-th row in the (k+1)th column is selected by the write row selecting ring pointer 62 and the write column selecting ring pointer 64 shown in FIG. 3, the potential on the write word line WWL.sub.n rises to an "H" level and the write column selecting signal WBS.sub.k+1 also rises to the "H" level. Consequently, the write selecting gate 12 in the n-th row in the (k+1)th column provides an output of the "H" level to turn the transistor 1 on. As a result, input data DI buffered by the write driver 11 is written to the storage capacitor 4 in the memory cell 10 over the write bit line WB.sub.k+1.
Thereupon, write column selecting signals WBS for all of the columns other than the (k+1)th column and potentials on the write word lines WWL for all of the rows other than the n-th row present the "L" level Consequently, all of the write selecting gates 12 other than the write selecting gate 12 in the n-th row in the (k+1)th column present the "L" level Accordingly, all of the transistors 1 of the memory cells 10 other than the memory cell 10 in the n-th row in the (k+1)th column remain in the off state so that information stored in the memory cells 10 is maintained.
In reading operation on the other hand, when a memory cell 10, for example, in the n-th row in the (k+1)th column is selected by the read row selecting ring pointer 63 and the read column selecting ring pointer 65, the potential on the read word line RWL.sub.n rises to the "H" level. Thereupon, all information stored in memory cells 10 in the n-th row is red out over the read bit lines RB.sub.1 to RB.sub.m. In this instance, however, output information is delivered only from the read circuit 13 for the (k+1)th column which is selected by the read column selecting signal RBS.sub.k+1.
A memory of the FIFO (first-in first-out) type which is a type of serial access memory which includes three-transistor type memory cells is disclosed in "Introduction to NMOS and CMOS VLSI System Design", pp. 268 to 273.
Such a conventional semiconductor memory device which includes three-transistor type memory cells as described above requires gate circuit for selecting a memory cell to which information is to be written.
Accordingly, the semiconductor memory device has a drawback that it requires a large scale for circuitry and a large occupation area due to the presence of such gate circuits.